Will be involved in all aspects of ASIC Implementation including low power synthesis, low power back end implementation, design for test (DFT) of complex SOC development flow including DFT architecture, Boundary Scan implementation, Memory BIST insertion, Scan insertion, ATPG pattern generation, verification of patterns and post silicon ATE support
Job Requirements :
Knowledge of high speed synthesis preferably (RTL compiler from Cadence).
DFT on complex SOC designs using industry standard DFT flows, preferably from Mentor Graphics
Hands-on experience on ASIC/SOC design, verification flows and methodologies
Knowledge of Boundary scan/JTAG/BSDL
Solid knowledge of Scan and BIST is essential
Understanding with Verilog/VHDL
Familiarity with Scan insertion/tracing
ATPG, stuck-at, at-speed coverage reporting/enhancement
Debugging skills with timing simulations
Formal verification and Lint tools experience desirable
Interface with RTL integration, PD and FV engineers to resolve/debug issues
Expertise in scripting language such as PERL, TCL is highly desirable
Experience in silicon bringup on ATE
Knowledge of ATE based silicon qualification and characterizationDebugging skills for convergence between DFT/functional vectors and ATE vectors
• BTech/MTech/MS in EE or equivalent with 10+ years of experience
Very good communication skills
Outstanding analytical and critical thinking skills.
Should lead a minimum of 10-15 team in a positive direction
Be a good contributor to the organization & a team player
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